Implementing a STARI chip

STARI is a high speed signaling technique that uses both synchronous and self timed circuits To demon strate STARI a chip has been fabricated using the MOSIS CMOS process In a simple test xture it operates at data rates of Mbits sec over a pair of wires Because STARI uses both synchronous and self timed circuits it provides an opportunity to compare these two design methods The synchronous circuits of the STARI chip achieve rates of operation two to three times those of the self timed circuits However the self timed FIFO in the receiver provides robust com pensation for clock skew that could not be achieved with synchronous circuitry alone Thus the STARI chip demonstrates advantages of combining these two design techniques